The present invention relates generally to the field of electronic imaging, and in particular, to an electronic camera having dual clocked line memory.
Many video cameras provide real-time digital processing of images from charge-coupled device (CCD) sensors. The signal processing circuits operate at the same clock frequencies as the sensor and are, therefore, unused during the sensor vertical transfer intervals. In a digital still camera, it is desirable to provide as high a frame rate as possible by reading out the image sensor data as quickly as possible, while still minimizing the clock frequency of the real-time digital processing circuitry, to minimize the cost and power consumption.
Commonly-assigned U.S. Pat. No. 5,016,107, entitled xe2x80x9cElectronic still camera utilizing image compression and digital storage,xe2x80x9d teaches an electronic camera that includes multiple image buffers to allow non-real time processing of the images. By storing the images in frame memories, it is possible to process previously captured images during the vertical transfer intervals associated with the readout of newly captured images. However, this design requires multiple, expensive frame memories and does not allow real-time processing of an image during the vertical transfer interval of that same image.
Accordingly, it is an object of the present invention to provide a digital image camera with increased throughput from the image sensor to image processing to final storage.
This object is achieved by an electronic camera for capturing and storing images, comprising:
(a) an image capture section including:
(i) an image sensor for capturing an image and producing pixel data representative of the captured image;
(ii) an analog-to-digital (A/D) converter for digitizing the pixel data; and
(iii) a horizontal shift register responsive to applied vertical clock signals for receiving lines of the pixel data from the image sensor and responsive to applied horizontal clock signals for sequentially transferring the lines of pixel data to the A/D converter, the time between the application of horizontal and vertical clock signals providing a vertical transfer interval wherein pixel data is prevented from being output from the horizontal shift register; and
(b) an image processing section including:
(i) a first-in-first-out (FIFO) memory coupled to the A/D converter for temporarily storing the digitized pixel data;
(ii) a digital signal processor coupled to the FIFO memory for processing the digitized pixel data; and
(iii) storage means coupled to the digital signal processor for storing the processed digitized pixel data;
(c) clock generator means for producing the vertical and horizontal clock signals and a FIFO write signal for causing the digitized pixel data from the A/D converter to be transferred to storage locations in the FIFO memory at a first frequency, and a master pixel clock signal;
(d) means responsive to the master pixel clock signal for producing a FIFO read signal for transferring the digitized pixel data from the FIFO memory to the digital signal processor at a second frequency for processing the digitized pixel data, and after processing, for transferring the processed pixel data to the storage means; and
(e) wherein the second frequency is selected to be lower than the first frequency.
An advantage of the present invention is to provide an effective way for an electronic camera to increase the throughput by changing the timing of various operating clocks. More particularly, during the time of vertical transfer, pixel data are transferred from the FIFO memory to the digital signal processor. Preferably, all of the pixel data in FIFO memory are transferred during this vertical transfer interval.
Another advantage of the present invention is that the digital signal processor can run slower, and therefore, can consume less power.